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PROFET(R) BTS 710 L1
Smart Four Channel Highside Power Switch
Features
* Overload protection * Current limitation * Short-circuit protection * Thermal shutdown * Overvoltage protection (including load dump) * Reverse battery protection1) * Undervoltage and overvoltage shutdown with auto-restart and hysteresis * Open drain diagnostic output * Open load detection in ON-state * CMOS compatible input * Loss of ground and loss of Vbb protection * Electrostatic discharge (ESD) protection
Product Summary Overvoltage Protection Operating voltage active channels: On-state resistance RON Nominal load current IL(NOM) Current limitation IL(SCr)
Vbb(AZ) 43 V Vbb(on) 5.0 ... 24 V two parallel four parallel one 200 100 50 m 1.9 2.8 4.4 A 5 5 5 A
Application
* C compatible power switch with diagnostic feedback for 12 V DC grounded loads * Most suitable for resistive and lamp loads * Replaces electromechanical relays and discrete circuits
General Description
N channel vertical power FET with charge pump, ground referenced CMOS compatible input and diagnostic feedback, monolithically integrated in Smart SIPMOS(R) technology. Fully protected by embedded protection functions. Pin Definitions and Functions Pin 1,10, 11,12, 15,16, 19,20 3 5 7 9 18 17 14 13 4 8 2 6 Symbol Function Positive power supply voltage. Design the Vbb wiring for the simultaneous max. short circuit currents from channel 1 to 4 and also for low thermal resistance IN1 Input 1 .. 4, activates channel 1 .. 4 in case of IN2 logic high signal IN3 IN4 OUT1 Output 1 .. 4, protected high-side power output OUT2 of channel 1 .. 4. Design the wiring for the OUT3 max. short circuit current OUT4 ST1/2 Diagnostic feedback 1/2 of channel 1 and channel 2, open drain, low on failure ST3/4 Diagnostic feedback 3/4 of channel 3 and channel 4, open drain, low on failure GND1/2 Ground 1/2 of chip 1 (channel 1 and channel 2) GND3/4 Ground 3/4 of chip 2 (channel 3 and channel 4) Pin configuration (top view) Vbb GND1/2 IN1 ST1/2 IN2 GND3/4 IN3 ST3/4 IN4 Vbb 1 2 3 4 5 6 7 8 9 10
*
20 19 18 17 16 15 14 13 12 11
Vbb Vbb OUT1 OUT2 Vbb Vbb OUT3 OUT4 Vbb Vbb
1)
With external current limit (e.g. resistor RGND=150 ) in GND connection, resistor in series with ST connection, reverse load current limited by connected load.
Semiconductor Group
1
06.96
BTS 710 L1 Block diagram
Four Channels; Open Load detection in on state;
Voltage source
Overvoltage protection
Current limit 1
+ V bb
Gate 1 protection
Leadframe
Channel 1
V Logic
Voltage sensor Level shifter Rectifier 1 Charge pump 1 Charge pump 2 Open load Short to Vbb detection 1 Current limit 2 Gate 2 protection Temperature sensor 1
OUT1
18
3 5 4
IN1 IN2
ESD
ST1/2
Logic
Channel 2
2
GND1/2
Level shifter Rectifier 2
OUT2
17
Load
Temperature sensor 2 Open load Short to Vbb detection 2
R R O1 O2 GND1/2 Load GND
Signal GND Chip 1
Chip 1
+ V bb Channel 3
Leadframe
Logic and protection circuit of chip 2 (equivalent to chip 1) 7 9 8
IN3 IN4 ST3/4
OUT3
14
Channel 4
OUT4
13
Load
6
GND3/4
PROFET
Signal GND Chip 2
(R)
R
R O3 O4 GND3/4 Load GND
Chip 2 Leadframe connected to pin 1, 10, 11, 12, 15, 16, 19, 20
Maximum Ratings at Tj = 25C unless otherwise specified Parameter Supply voltage (overvoltage protection see page 4) Supply voltage for full short circuit protection Tj,start = -40 ...+150C Symbol Values 43 24 Unit V V
Vbb Vbb
Semiconductor Group
2
BTS 710 L1
Maximum Ratings at Tj = 25C unless otherwise specified Parameter Load current (Short-circuit current, see page 5) Load dump protection2) VLoadDump = UA + Vs, UA = 13.5 V RI3) = 2 , td = 200 ms; IN = low or high, each channel loaded with RL = 7.1 , Operating temperature range Storage temperature range Power dissipation (DC)5 Ta = 25C: (all channels active) Ta = 85C: Electrostatic discharge capability (ESD) (Human Body Model) Input voltage (DC) Current through input pin (DC) Current through status pin (DC)
see internal circuit diagram page 8
Symbol
Values self-limited 60 -40 ...+150 -55 ...+150 3.6 1.9 1.0 -10 ... +16 2.0 5.0
Unit A V C W kV V mA
IL VLoad dump4) Tj Tstg Ptot VESD VIN IIN IST
Thermal resistance junction - soldering point5),6) junction - ambient5)
each channel: one channel active: all channels active:
Rthjs Rthja
16 44 35
K/W
Electrical Characteristics
Parameter and Conditions, each of the four channels
at Tj = 25 C, Vbb = 12 V unless otherwise specified
Symbol
Values min typ max
Unit
Load Switching Capabilities and Characteristics On-state resistance (Vbb to OUT) IL = 1.8 A each channel, Tj = 25C: RON Tj = 150C: two parallel channels, Tj = 25C: four parallel channels, Tj = 25C:
--
165 320 83 42
200 400 100 50
m
2)
3) 4) 5) 6)
Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins, e.g. with a 150 resistor in the GND connection and a 15 k resistor in series with the status pin. A resistor for input protection is integrated. RI = internal resistance of the load dump test pulse generator VLoad dump is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839 Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70m thick) copper area for Vbb connection. PCB is vertical without blown air. See page 14 Soldering point: upper side of solder edge of device pin 15. See page 14
Semiconductor Group
3
BTS 710 L1
Parameter and Conditions, each of the four channels
at Tj = 25 C, Vbb = 12 V unless otherwise specified
Symbol
Values min typ max 1.7 2.6 4.1 -80 80 0.1 0.1 1.9 2.8 4.4 -200 200 ----
Unit
one channel active: two parallel channels active: four parallel channels active: 5), T = 85C, T 150C Device on PCB a j Output current while GND disconnected or pulled up; Vbb = 30 V, VIN = 0, see diagram page 9 Turn-on time to 90% VOUT: Turn-off time to 10% VOUT: RL = 12 , Tj =-40...+150C Slew rate on 10 to 30% VOUT, RL = 12 , Tj =-40...+150C: Slew rate off 70 to 40% VOUT, RL = 12 , Tj =-40...+150C: Operating Parameters Operating voltage7) Undervoltage shutdown Undervoltage restart
Nominal load current
IL(NOM)
A
IL(GNDhigh) ton toff
dV/dton -dV/dtoff
10 400 400 1 1
mA s
V/s V/s
Tj =-40...+150C: Tj =-40...+150C: Tj =-40...+25C: Tj =+150C: Undervoltage restart of charge pump see diagram page 13 Tj =-40...+150C: Undervoltage hysteresis Vbb(under) = Vbb(u rst) - Vbb(under) Overvoltage shutdown Tj =-40...+150C: Overvoltage restart Tj =-40...+150C: Overvoltage hysteresis Tj =-40...+150C: 8) Overvoltage protection Tj =-40...+150C: I bb = 40 mA Standby current, all channels off Tj =25C: VIN = 0 Tj =150C: Leakage output current (included in Ibb(off)) VIN = 0 Operating current 9), VIN = 5V, Tj =-40...+150C IGND = IGND1/2 + IGND3/4, one channel on: four channels on:
Vbb(on) Vbb(under) Vbb(u rst) Vbb(ucp)
Vbb(under)
5.0 3.5 ---24 23 -42 ----
---5.6 0.2 --0.5 47 28 44 --
24 5.0 5.0 7.0 7.0 -34 ---60 70 12
V V V V V V V V V A A
Vbb(over) Vbb(o rst) Vbb(over) Vbb(AZ) Ibb(off) IL(off)
IGND
---
2 8
3 12
mA
7) 8) 9)
At supply voltage increase up to Vbb = 5.6 V typ without charge pump, VOUT Vbb - 2 V see also VON(CL) in circuit diagram on page 8. Add IST, if IST > 0
Semiconductor Group
4
BTS 710 L1
Parameter and Conditions, each of the four channels
at Tj = 25 C, Vbb = 12 V unless otherwise specified
Symbol
Values min typ max
Unit
Protection Functions Initial peak short circuit current limit, (see timing
diagrams, page 11)
each channel, Tj =-40C: IL(SCp) 8 11.5 15 6 9 12 Tj =25C: 3.5 6 7.5 Tj =+150C: two parallel channels twice the current of one channel four parallel channels four times the current of one channel Repetitive short circuit current limit, Tj = Tjt each channel IL(SCr) -5 --5 -two parallel channels -5 -four parallel channels
(see timing diagrams, page 11)
A
A
Initial short circuit shutdown time
Tj,start =-40C: toff(SC) Tj,start = 25C: Tjt Tjt
--150 --
5.5 4 -10
-----
ms
(see page 10 and timing diagrams on page 11)
Thermal overload trip temperature Thermal hysteresis Reverse Battery Reverse battery voltage 10) Drain-source diode voltage (Vout > Vbb) IL = - 1.9 A, Tj = +150C
C K
-Vbb -VON
---
-610
32 --
V mV
Diagnostic Characteristics Open load detection current, (on-condition) 10 -200 each channel, Tj = -40C: I L (OL)4 10 -150 Tj = 25C: 10 -150 Tj = +150C: twice the current of one channel two parallel channels four times the current of one channel four parallel channels 11) Open load detection voltage 2 3 4 Tj =-40..+150C: VOUT(OL) Internal output pull down 4 10 30 (OUT to GND), VOUT = 5 V Tj =-40..+150C: RO
mA
V k
Requires a 150 resistor in GND connection. The reverse load current through the intrinsic drain-source diode has to be limited by the connected load. Note that the power dissipation is higher compared to normal operating conditions due to the voltage drop across the intrinsic drain-source diode. The temperature protection is not active during reverse current operation! Input and Status currents have to be limited (see max. ratings page 3 and circuit page 8). 11) External pull up resistor required for open load detection in off state.
10)
Semiconductor Group
5
BTS 710 L1
Parameter and Conditions, each of the four channels
at Tj = 25 C, Vbb = 12 V unless otherwise specified
Symbol
Values min typ max
Unit
Input and Status Feedback12) Input resistance
(see circuit page 8)
Tj =-40..+150C: Tj =-40..+150C:
RI VIN(T+) VIN(T-)
VIN(T) IIN(off)
2.5 1.7 1.5 -1 20 100 ---
3.5 --0.5 -50 320 5 200
6 3.5 --50 90 800 20 600
k V V V A A s s s
Input turn-on threshold voltage Input turn-off threshold voltage
Tj =-40..+150C:
Input threshold hysteresis VIN = 0.4 V: Off state input current Tj =-40..+150C: VIN = 5 V: On state input current Tj =-40..+150C: Delay time for status with open load after switch off (other channel in off state) Tj =-40..+150C: (see timing diagrams, page 12), Delay time for status with open load after switch off (other channel in on state) Tj =-40..+150C: (see timing diagrams, page 12), Status invalid after positive input slope Tj =-40..+150C: (open load) Status output (open drain) Zener limit voltage Tj =-40...+150C, IST = +1.6 mA: ST low voltage Tj =-40...+25C, IST = +1.6 mA: Tj = +150C, IST = +1.6 mA:
IIN(on) td(ST OL4) td(ST OL5) td(ST)
VST(high) VST(low)
5.4 ---
6.1 ---
-0.4 0.6
V
12)
If ground resistors RGND are used, add the voltage drop across these resistors.
Semiconductor Group
6
BTS 710 L1 Truth Table
Channel 1 and 2 Channel 3 and 4 (equivalent to channel 1 and 2) Chip 1 Chip 2
IN1 IN3 IN2 IN4 OUT1 OUT3 OUT2 OUT4 ST1/2 ST3/4 BTS 710L1 BTS 711L1 H H H H H(L13)) H L H(L13)) H L L14) H H(L15)) L14) H H(L15)) H L L H L H L H ST1/2 ST3/4 BTS 712N1 H H H H L H H L H H L14) H H L14) H H H L L H L H L H
Normal operation
Open load
Channel 1 (3)
Channel 2 (4)
Short circuit to Vbb
Channel 1 (3)
Channel 2 (4)
Overtemperature
both channel
Channel 1 (3) Channel 2 (4) Undervoltage/ Overvoltage
L L H H L L H L H X L L H L H X L X H L H X X X
L H L H L H X L L H L H X L L H L H X X X L H X
L L H H Z Z H L H X H H H L H X L L L L L X X L
L H L H L H X Z Z H L H X H H H L L L X X L L L
L = "Low" Level H = "High" Level
X = don't care Z = high impedance, potential depends on external circuit Status signal valid after the time delay shown in the timing diagrams
Parallel switching of channel 1 and 2 (also channel 3 and 4) is easily possible by connecting the inputs and outputs in parallel (see truth table). If switching channel 1 to 4 in parallel, the status outputs ST1/2 and ST3/4 have to be configured as a 'Wired OR' function with a single pull-up resistor.
Terms
V Ibb bb Leadframe I IN1 I IN2 I ST1/2 V IN1 VIN2 VST1/2 3 5 4 IN1 IN2 Vbb OUT1 PROFET Chip 1 18 V ON1 V ON2 I L1 I IN4 I L2 V OUT1 I GND1/2 R GND1/2 VOUT2 R GND3/4 I ST3/4 V IN3 VIN4 VST3/4 Leadframe I IN3 7 9 8 IN3 IN4 Vbb OUT3 PROFET Chip 2 14 VON3 V ON4 I L3 I L4 V OUT3 IGND3/4 VOUT4
OUT2
17
OUT4
13
ST1/2 GND1/2 2
ST3/4 GND3/4 6
Leadframe (Vbb) is connected to pin 1,10,11,12,15,16,19,20 External RGND optional; two resistors RGND1/2 ,RGND3/4 = 150 or a single resistor RGND = 75 for reverse battery protection up to the max. operating voltage.
13) 14)
With additional external pull up resistor An external short of output to Vbb in the off state causes an internal current from output to ground. If R GND is used, an offset voltage at the GND and ST pins will occur and the VST low signal may be errorious. 15) Low resistance to V may be detected by no-load-detection bb
Semiconductor Group
7
BTS 710 L1
Input circuit (ESD protection), IN1...4
R IN I
RI Logic
V Z2
Overvoltage protection of logic part
GND1/2 or GND3/4
+ V bb
ESD-ZD I GND
IN
I
I
IN
R ST
ST
ESD zener diodes are not to be used as voltage clamp at DC conditions. Operation in this mode may result in a drift of the zener voltage (increase of up to 1 V).
V
Z1 GND
R GND
Status output, ST1/2 or ST3/4
+5V
Signal GND
VZ1 = 6.1 V typ., VZ2 = 47 V typ., RI = 3.5 k typ., RGND = 150
R ST(ON)
ST
Reverse battery protection
+ 5V - Vbb
GND
ESDZD
R ST
IN ST
ESD-Zener diode: 6.1 V typ., max 5.0 mA; RST(ON) < 380 at 1.6 mA, ESD zener diodes are not to be used as voltage clamp at DC conditions. Operation in this mode may result in a drift of the zener voltage (increase of up to 1 V).
RI OUT
Power Inverse Diode
Logic
GND
overvoltage output clamp, OUT1...4
+Vbb VZ
RGND
Signal GND
RL
Power GND
RGND = 150 , RI = 3.5 k typ,
Temperature protection is not active during inverse current operation.
V ON OUT
PROFET
Power GND
VON clamped to VON(CL) = 47 V typ.
Semiconductor Group
8
BTS 710 L1
Open-load detection, OUT1...4 ON-state diagnostic condition: VON < RON*IL(OL); IN high
+ V bb
GND disconnect with GND pull up
(channel 1/2 or 3/4)
IN1 V IN1 IN2 V
Vbb OUT1 PROFET OUT2
ON
VON
IN2 ST GND
OUT
Logic unit
Open load detection
V
V bb
ST
V
GND
If VGND > VIN - VIN(T+) device stays off Due to VGND > 0, no VST = low signal available.
OFF-state diagnostic condition: VOUT > 3 V typ.; IN low
R
EXT
OFF
V OUT
Logic unit
Open load detection
R
O
Signal GND
GND disconnect
(channel 1/2 or 3/4)
Ibb bb IN1 IN2 ST Vbb OUT1 PROFET OUT2 GND V GND
V
V
V V IN1 IN2 ST
In case of IN = high is VOUT VIN - VIN(T+). Due to VGND > 0, no VST = low signal available.
Semiconductor Group
9
BTS 710 L1
Typ. on-state resistance
RON = f (Vbb,Tj ); IL = 1.8 A, IN = high RON [mOhm] 500
450 400 350 300 250 200 150 100 50 0 0 5 10 15 20 25 30 35 0 -50 85C 25C -40C 10 30 Tj = 150C 50
Typ. standby current
Ibb(off) = f (Tj ); Vbb = 9...24 V, IN1...4 = low Ibb(off) [A] 60
40
20
0
50
100
150
200
Vbb [V]
Tj [C]
Typ. open load detection current
IL(OL) = f (Vbb,Tj ); IN = high IL(OL) [mA] 140
-40C 120 no load detection not specified for V bb < 6V 25C
Typ. initial short circuit shutdown time
toff(SC) = f (Tj,start ); Vbb =12 V toff(SC) [msec] 6
5
100
4 85C Tj = 150C 3
80
60
2
40
20
1
0 0 5 10 15 20 25
0 -50
0
50
100
150
200
Vbb [V]
Tj,start [C]
Semiconductor Group
10
BTS 710 L1
Timing diagrams
Timing diagrams are shown for chip 1 (channel 1/2). For chip 2 (channel 3/4) the diagrams are valid too. The channels 1 and 2, respectively 3 and 4, are symmetric and consequently the diagrams are valid for each channel as well as for permuted channels
Figure 1a: Vbb turn on:
IN1 IN2
Figure 3a: Turn on into short circuit: shut down by overtemperature, restart by cooling
IN1 other channel: normal operation
V bb I V
OUT1 L1
I
L(SCp) I L(SCr)
V
OUT2
t ST open drain t ST
off(SC)
t
Heating up of the chip may require several milliseconds, depending on external conditions (toff(SC) vs. Tj,start see page 10)
Figure 2a: Switching a lamp:
IN
Figure 3b: Turn on into short circuit: shut down by overtemperature, restart by cooling (two parallel switched channels 1 and 2)
IN1/2
ST I V
L1
+I
L2
I L(SCp)
OUT
I
I L(SCr)
L
t ST1/2
The initial peak current should be limited by the lamp and not by the initial short circuit current IL(SCp) = 9 A typ. of the device.
t
off(SC)
t
Semiconductor Group
11
BTS 710 L1
Figure 4a: Overtemperature: Reset if Tj IN
Figure 5b: Open load: detection in ON-state, turn on/off to open load
IN1
IN2 ST V
OUT1
channel 2: normal operation
V
OUT
I T
L1
channel 1: open load
J
t
d(ST)
t
d(ST OL4)
t
d(ST)
t
d(ST OL5)
t
ST t
The status delay time td(STOL4) allows to distinguish between the failure modes "open load in ON-state" and "overtemperature".
Figure 5a: Open load: detection in ON-state, open load occurs in on-state
IN1
Figure 5c: Open load: detection in ON- and OFF-state (with REXT), turn on/off to open load
IN1
IN2
channel 2: normal operation
IN2
channel 2: normal operation
VOUT1
V
OUT1
I L1
channel 1: open load t d(ST OL1)
normal load
open load
I L1
channel 1: open load
t d(ST OL2)
t d(ST OL1)
t
d(ST OL2)
ST
t d(ST)
t
d(ST)
t d(ST OL5) t
ST t
td(ST OL1) = 30 s typ., td(ST OL2) = 20 s typ td(ST OL5) depends on external circuitry because of high impedance
Semiconductor Group
12
BTS 710 L1
Figure 6a: Undervoltage: Figure 7a: Overvoltage:
IN
IN
V bb V
bb(under)
Vbb Vbb(u cp) Vbb(u rst) V
V ON(CL)
Vbb(over)
V bb(o rst)
OUT
V OUT
ST open drain t
ST
t
Figure 6b: Undervoltage restart of charge pump
V on VON(CL)
off-state
on-state
V
bb(over)
V
V V
bb(u rst)
bb(o rst)
bb(u cp)
V
bb(under)
IN = high, normal load conditions. Charge pump starts at Vbb(ucp) = 5.6 V typ.
Semiconductor Group
off-state
V bb
13
BTS 710 L1
Package and Ordering Code
Standard P-DSO-20-9
BTS710L1 Ordering Code Q67060-S7004-A2
All dimensions in millimetres 1) Does not include plastic or metal protrusions of 0.15 max per side 2) Does not include dambar protrusion of 0.05 max per side
Definition of soldering point with temperature Ts: upper side of solder edge of device pin 15.
Pin 15
Printed circuit board (FR4, 1.5mm thick, one layer 70m, 6cm2 active heatsink area) as a reference for max. power dissipation Ptot, nominal load current IL(NOM) and thermal resistance Rthja
Semiconductor Group
14

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